1. Field of the Invention
The present invention relates to a liquid crystal display, and more particularly to a gate driving apparatus and a gate driving method in a liquid crystal display.
2. Discussion of the Related Art
In general, a liquid crystal display (LCD) controls a light transmittance of a liquid crystal using an electric field to thereby display a picture.
FIG. 1 is a schematic view of a configuration of a an active matrix liquid crystal display device in accordance with the related art. Referring to FIG. 1, the active matrix LCD includes a liquid crystal display panel 13. The LCD panel 13 comprises (m×n) liquid crystal cells Clc in a matrix arrangement, m data lines D1 to Dm and n gate lines G1 to Gn intersecting each other. TFT's are provided at the intersections thereof of the data lines and the gate lines. The LCD panel includes a data driving circuit 11 for applying data to the data lines D1 to Dm of the liquid crystal display panel 13. The LCD panel 13 also includes a gate driving circuit 12 for applying a scanning pulse to the gate lines G1 to Gn.
The liquid crystal display panel has liquid crystal molecules injected between two glass substrates. The data lines D1 to Dm and the gate lines G1 to Gn, which cross each other perpendicularly, are provided at the lower glass substrate of the liquid crystal display panel 13. The TFT provided at each intersection between the data lines D1 to Dm and the gate lines G1 to Gn applies a data voltage supplied via the data line D1 to Dn to the liquid crystal cell Clc in response to a scanning pulse from the gate line G1 to Gn. To this end, the gate electrode of the TFT is connected to the gate line G1 to Gn while the drain electrode thereof is connected to the data line D1 to Dm. Further, the source electrode of the TFT is connected to a pixel electrode of the liquid crystal cell Clc.
The upper glass substrate of the liquid crystal display panel 13 is provided with black matrix, color filters and common electrode (not shown). Polarizers having a perpendicular light axis are attached onto the upper and lower glass substrates of the liquid crystal display panel 13, and an alignment film for establishing a free-tilt angle of the liquid crystal is provided at the inner side thereof tangent to the liquid crystal.
The liquid crystal cell Clc of the liquid crystal display panel 13 is provided with a storage capacitor Cst. The storage capacitor Cst is provided between the pixel electrode of the liquid crystal cell Clc and the pre-stage gate line or between the pixel electrode of the liquid crystal cell Clc and a common electrode line (not shown), thereby constantly keeping a voltage of the liquid crystal cell Clc.
The data driving circuit 1 comprises a plurality of data driving integrated circuits. Each of the data driving integrated circuits includes a shift register, a latch, a digital to analog converter and an output buffer. The data driving circuit 11 latches a digital video data, and converts the digital video data to an analog gamma compensation voltage to thereby apply it to the data lines D1 to Dm.
The gate driving circuit 12 comprises a plurality of gate driving integrated circuits. Each of the gate driving integrated circuits includes a shift register for sequentially shifting a start pulse every one horizontal period to generate a scanning pulse, a level shifter for converting an output signal of the shift register to a swing width suitable for a driving of the liquid crystal cell Clc, and an output buffer connected between the level shifter and the gate line G1 to Gn. The gate driving circuit 12 sequentially applies the scanning pulse to the gate lines G1 to Gn to select a horizontal line of the liquid crystal display panel 13 supplied with a data.
FIG. 2 is a waveform diagram of driving signals and data voltages applied to the liquid crystal cells of the liquid crystal display panel in accordance with the related art. In FIG. 2, ‘Vd’ represents a data voltage outputted by the data driving circuit 11 and applied to the data lines D1 to Dm. ‘Vlc’ represents a data voltage charged and discharged in and from the liquid crystal cell Clc. Further, ‘Scp’ represents a scanning pulse generated in one horizontal period. ‘Vcom’ represents a common voltage applied to the common electrode of the liquid crystal cell Clc.
FIG. 3 is a circuit diagram of a shift register of a gate driving circuit in accordance with the related art. In FIG. 3, the shift register comprises n stages 31 to 3n connected in cascade. A level shifter and an output buffer (not shown) are provided between the stages 31 to 3n and the gate lines G1 to Gn.
In the shift register depicted in FIG. 3, a start pulse SP is inputted to the first stage 21. Output signals g1 to gn−1 from stages 1 to n−1 are inputted as start pulses to the second to nth stages 22 to 2n, respectively. Further, each stage 21 to 2n has the same circuit configuration, and shifts the start pulse SP or the output signals g1 to gn−1 of the previous stage in response to two clock signals of four clock signals C1 to C4, thereby generating a scanning pulse. The generated scanning pulse has a pulse width of one horizontal period.
FIG. 4 is a detailed circuit diagram of a stage circuit configuration of the shift register in accordance with the related art. FIG. 4 depicts a detailed circuit configuration of i-th stage 2i (wherein i is an integer ranging from 1 to n) in the shift register shown in FIG. 3. Stage 2i includes a fifth NMOS transistor T5 for applying a high logical voltage signal to an output node 3i, and a sixth NMOS transistor T6 for applying a low logical voltage signal to an output node 4i. 
FIG. 5 is a waveform diagram of input signals of the stage circuit and signals at a control node and an output node in accordance with the related art. An operation of stage 2i will be described in reference to FIG. 4 and FIG. 5.
During a time interval t1, the first and second clock signals C1 and C2 remain at a low logical voltage. The start pulse SP or the output signal gi−1 of the previous stage having a high logical voltage is applied to the gate electrodes of the first and fourth NMOS transistors T1 and T4 to thereby turn on the first and fourth NMOS transistors T1 and T4. A voltage VP1 at a first node P1 is raised to a middle voltage to turn on the fifth NMOS transistor T5, but a voltage Vouti at the output node 3i remains at a low logical voltage because the first clock signal C1 remains at a low logical voltage. A turning-on of the fourth NMOS transistor T4 lowers a voltage at a second node P2 to turn off the second and sixth NMOS transistors T2 and T6, thereby shutting off a discharge path of the first node P1.
During a time interval t2, the first clock signal C1 is inverted to a high logical voltage while the start pulse SP and the output signal gi−1 of the previous stage are inverted to a low logical voltage. The first and fourth NMOS transistors T1 and T4 are turned off. The voltage VP1 at the first node P1 is increased by a voltage charged in a parasitic capacitor between the drain electrode and the gate electrode of the fifth NMOS transistor supplied with a high logical voltage of the first clock signal C1. Thereby, the voltage VP1 is raised beyond a threshold voltage of the fifth NMOS transistor T5. In other words, the voltage VP1 at the first node P1 becomes higher during time interval t2 than during than time interval t1 due to a bootstrapping effect. Thus, during time interval t2, the fifth NMOS transistor T5 is turned on. The voltage Vouti at the output node 3i is driven by a voltage of the first clock signal C1 supplied by a conduction of the fifth NMOS transistor T3. Consequently, voltage Vouti is inverted to a high logical voltage.
During a time interval t3 interval, the first clock signal C1 is inverted to a low logical voltage. The fifth NMOS transistor T5 remains in an on-state. A voltage Vout at the output node 4i is inverted to a low logic voltage while being discharged via the fifth NMOS transistor T5. Concurrently, a voltage VP1 at the first node P1 is lowered to a middle voltage.
During a time interval t4, the third clock signal C3 is inverted to a high logical voltage. The third NMOS transistor T3 is turned on in response to the third clock signal C3, and a high-level supply voltage VDD is applied, via the third NMOS transistor T3, to the second node P2 to thereby raises a voltage VP2 at the second node P2. The rising voltage VP2 at the second node P2 turns on the sixth NMOS transistor T6 to discharge a voltage Vouti at the output node 3i to a ground voltage VSS. Concurrently, the voltage VP2 turns on the second NMOS transistor T2 to discharge the voltage VP1 at the first node P1 to the ground voltage VSS.
However, the related art LCD has a problem in that it has a high manufacturing cost caused by the multitude of data lines D1 to Dm provided at the liquid crystal display panel 13 and the multitude of driving integrated circuits of the data driving circuit 11 for supplying a data voltage to the data lines D1 to Dm. Such a problem becomes more serious as a resolution goes higher and the liquid crystal display panel 13 has a larger dimension.